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SI5322
P R E L I M I N A R Y D A TA S H E E T
PI N - PROGRAMMABLE PR E C I S I O N C L O C K MU L T I P L I E R
Description
The SI5322 is a low jitter, precision clock multiplier for high-speed communication systems, including SONET OC-48/OC-192, Ethernet, and Fibre Channel. The SI5322 accepts dual clock inputs ranging from 19.44 to 707 MHz and generates two equal frequencymultiplied clock outputs ranging from 19.44 to 1050 MHz. The input clock frequency and clock multiplication ratio are selectable from a table of popular SONET, Ethernet, and Fibre Channel rates. The SI5322 is based on Silicon Laboratories' 3rdgeneration DSPLL(R) technology, which provides anyrate frequency synthesis in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V supply, the SI5322 is ideal for providing clock multiplication in high performance timing applications.
Features
Selectable output frequencies ranging from 19.44 to 1050 MHz Low jitter clock outputs with jitter generation as low as 0.6 psRMS (50 kHz-80 MHz) Integrated loop filter with selectable loop bandwidth (30 kHz to 1.3 MHz) Dual clock inputs with manual or automatically controlled hitless switching Dual clock outputs with selectable signal format: LVPECL, LVDS, CML, CMOS Support for ITU G.709 FEC ratios (255/238, 255/237, 255/236) LOS alarm output Pin-controlled output phase adjust Pin-programmable settings On-chip voltage regulator for 1.8, 2.5, or 3.3 V 10% operation Small size: 6 x 6 mm 36-lead QFN Pb-free, RoHS compliant
Applications
SONET/SDH OC-48/OC-192 line cards GbE/10GbE, 1/2/4/8/10GFC line cards ITU G.709 line cards Optical modules Test and measurement
CKIN1
CKOUT1
DSPLL
CKIN2
(R)
Signal Format CKOUT2 Disable/BYPASS
Loss of Signal
Signal Detect
Control VDD (1.8, 2.5, or 3.3 V) GND Frequency Select Manual/Auto Switch Clock Select
Bandwidth Select
Preliminary Rev. 0.47 7/07
Copyright (c) 2007 by Silicon Laboratories
SI5322
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
SI5322
Table 1. Performance Specifications
(VDD = 1.8, 2.5, or 3.3 V 10%, TA = -40 to 85 C)
Parameter Temperature Range Supply Voltage
Symbol TA VDD
Test Condition
Min -40 2.97 2.25 1.62
Typ 25 3.3 2.5 1.8 251 217 204 194 TBD --
Max 85 3.63 2.75 1.98 279 243 234 220 TBD 707.35
Unit C V V V mA mA mA mA mA MHz
Supply Current
IDD
fOUT = 622.08 MHz Both CKOUTs enabled LVPECL format output CKOUT2 disabled fOUT = 19.44 MHz Both CKOUTs enabled CMOS format output CKOUT2 disabled Tristate/Sleep Mode
-- -- -- -- -- 19.44
Input Clock Frequency (CKIN1, CKIN2) Output Clock Frequency (CKOUT1, CKOUT2)
CKF CKOF
Input frequency and clock multiplication ratio pin-selectable from table of values using FRQSEL and FRQTBL settings. Consult Silicon Laboratories configuration software DSPLLsim or Any-Rate Precision Clock Family Reference Manual at www.silabs.com/clock for table selections.
19.44
--
1049.76
MHz
Input Clocks (CKIN1, CKIN2) Differential Voltage Swing Common Mode Voltage CKNDPP CKNVCM 1.8 V 10% 2.5 V 10% 3.3 V 10% Rise/Fall Time Duty Cycle CKNTRF CKNDC 20-80% Whichever is less 0.25 0.9 1.0 1.1 -- 40 50 VDD - 1.42 1.1 0.5 -- -- -- -- -- -- -- -- -- -- 1.9 1.4 1.7 1.95 11 60 -- VDD - 1.25 1.9 0.93 VPP V V V ns % ns V V V
Output Clocks (CKOUT1, CKOUT2) Common Mode Differential Output Swing Single Ended Output Swing VOCM VOD VSE LVPECL 100 load line-to-line
Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing.
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Preliminary Rev. 0.47
SI5322
Table 1. Performance Specifications (Continued)
(VDD = 1.8, 2.5, or 3.3 V 10%, TA = -40 to 85 C)
Parameter Rise/Fall Time Duty Cycle PLL Performance Jitter Generation
Symbol CKOTRF CKODC JGEN
Test Condition 20-80%
Min -- 45
Typ 230 --
Max 350 55
Unit ps %
fo = 622.08 MHz, LVPECL output format 50 kHz - 80 MHz 12 kHz - 20 MHz
-- -- --
0.6 0.6 0.05 TBD TBD TBD TBD TBD TBD TBD
TBD TBD 0.1 TBD TBD TBD TBD TBD TBD TBD
ps rms ps rms dB dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc dBc
Jitter Transfer Phase Noise
JPK CKOPN fOUT = 622.08 MHz 100 Hz offset 1 kHz offset 10 kHz offset 100 kHz offset 1 MHz offset
-- -- -- -- -- -- --
Subharmonic Noise Spurious Noise Package Thermal Resistance Junction to Ambient
SPSUBH SPSPUR
Phase Noise @ 100 kHz Offset Max spur @ n x F3 (n > 1, n x F3 < 100 MHz)
JA
Still Air
--
38
--
C/W
Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing.
Table 2. Absolute Maximum Ratings
Parameter DC Supply Voltage LVCMOS Input Voltage Operating Junction Temperature Storage Temperature Range ESD HBM Tolerance (100 pF, 1.5 k) ESD MM Tolerance Latch-Up Tolerance Symbol VDD VDIG TJCT TSTG Value -0.5 to 3.6 -0.3 to (VDD + 0.3) -55 to 150 -55 to 150 2 200 JESD78 Compliant Unit V V C C kV V
Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability.
Preliminary Rev. 0.47
3
SI5322
C4 1 F System Power Supply C3 0.1 F Ferrite Bead C2 0.1 F C1 0.1 F 130 CKIN1+ CKIN1- 82 82 CKOUT2+ VDD = 3.3 V CKOUT2- 130 130 CKIN2+ CKIN2- 82 82 C1B C2B CKIN_1 Loss of Signal CKIN_2 Loss of Signal
VDD = 3.3 V
GND
VDD
130
CKOUT1+
0.1 F 100
+
CKOUT1-
0.1 F 0.1 F 100 0.1 F
- Clock Outputs +
Input Clock Sources1
-
SI5322
Manual/Automatic Clock Selection (L) Input Clock Select/ Active Clock Indicator Frequency Table Select Frequency Select Bandwidth Select Signal Format Select Clock Output 2 Disable/ Bypass Mode Control Reset
AUTOSEL2 CS_CA3 FRQTBL2 FRQSEL[3:0]2 BWSEL[1:0]2 SFOUT[1:0]2 DBL2_BY2 RST
Notes: 1. Assumes differential LVEPECL termination (3.3 V) on clock inputs.
2. Denotes tri-level input pins with states designated as L (ground), M (VDD/2), and H (VDD). 3. Assumes manual input clock selection.
Figure 1. SI5322 Typical Application Circuit
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Preliminary Rev. 0.47
SI5322
1. Functional Description
The SI5322 is a low jitter, precision clock multiplier for high-speed communication systems, including SONET OC-48/OC-192, Ethernet, and Fibre Channel. The SI5322 accepts dual clock inputs ranging from 19.44 to 707 MHz and generates two frequency-multiplied clock outputs ranging from 19.44 to 1050 MHz. The two input clocks are at the same frequency and the two output clocks are at the same frequency. The input clock frequency and clock multiplication ratio are selectable from a table of popular SONET, Ethernet, and Fibre Channel rates. In addition to providing clock multiplication in SONET and datacom applications, the SI5322 supports SONET-to-datacom frequency translations. Silicon Laboratories offers a PC-based software utility, DSPLLsim, that can be used to look up valid SI5322 frequency translations. This utility can be downloaded from www.silabs.com/timing. This information is also available in the Any-Rate Precision Clock Family Reference Manual, also available from www.silabs.com/timing. The SI5322 is recommended for applications in which the input clock is relatively low jitter and only clock multiplication is required. The SI5322 is based on Silicon Laboratories' 3rd-generation DSPLL(R) technology, which provides any-rate frequency synthesis in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The SI5322 PLL loop bandwidth is selectable via the BWSEL[1:0] pins and supports a range from 30 kHz to 1.5 MHz. The DSPLLsim software utility can be used to calculate valid loop bandwidth settings for a given input clock frequency/clock multiplication ratio. The SI5322 monitors all input clocks for loss of signal and provides a LOS alarm when it detects a missing clock. In the case when the input clocks enter alarm conditions, the PLL will freeze the DCO output frequency near its last value to maintain operation with an internal state close to the last valid operating state. The SI5322 has two differential clock outputs. The electrical format of the clock outputs is programmable to support LVPECL, LVDS, CML, or CMOS loads. If not required, the second clock output can be powered down to minimize power consumption. The phase difference between the selected input clock and the output clocks is adjustable in 200 ps increments for system skew control. For system-level debugging, a bypass mode is available which drives the output clock directly from the input clock, bypassing the internal DSPLL. The device is powered by a single 1.8, 2.5, or 3.3 V supply.
1.1. Further Documentation
Consult the Silicon Laboratories Any-Rate Precision Clock Family Reference Manual (FRM) for more detailed information about the SI5322. The FRM can be downloaded from www.silabs.com/timing. Silicon Laboratories has developed a PC-based software utility called DSPLLsim to simplify device configuration, including frequency planning and loop bandwidth selection. This utility can be downloaded from www.silabs.com/timing.
Preliminary Rev. 0.47
5
SI5322
2. Pin Descriptions: SI5322
CKOUT1- CKOUT2+ CKOUT2- GND CKOUT1+ 27 FRQSEL3 26 FRQSEL2 25 FRQSEL1 24 FRQSEL0 23 BWSEL1 22 BWSEL0 21 CS_CA 20 NC 19 NC 10 11 12 13 14 15 16 17 18 CKIN2- CKIN1- VDD VDD DBL2_BY CKIN2+ VDD CKIN1+ NC SFOUT0 SFOUT1 VDD
36 35 34 33 32 31 30 29 28 RST FRQTBL C1B C2B VDD GND NC GND AUTOSEL 1 2 3 4 5 6 7 8 9
NC
GND Pad
Pin assignments are preliminary and subject to change. Pin # Pin Name I/O Signal Level
Table 3. SI5322 Pin Descriptions
Description External Reset. Active low input that performs external hardware reset of device. Resets all internal logic to a known state. Clock outputs are tristated during reset. After rising edge of RST signal, the SI5322 will perform an internal self-calibration. This pin has a weak pull-up. Frequency Table Select. Selects SONET/SDH, datacom, or SONET/SDH to datacom frequency table. L = SONET/SDH. M = Datacom. H = SONET/SDH to Datacom. This pin has a weak pull-down. CKIN1 Loss of Signal. Active high loss-of-signal indicator for CKIN1. Once triggered, the alarm will remain active until CKIN1 is validated. 0 = CKIN1 present. 1 = LOS on CKIN1. CKIN2 Loss of Signal. Active high loss-of-signal indicator for CKIN2. Once triggered, the alarm will remain active until CKIN2 is validated. 0 = CKIN2 present. 1 = LOS on CKIN2.
1
RST
I
LVCMOS
2
FRQTBL
I
3-Level
3
C1B
O
LVCMOS
4
C2B
O
LVCMOS
6
Preliminary Rev. 0.47
SI5322
Table 3. SI5322 Pin Descriptions (Continued)
Pin # Pin Name I/O Signal Level Description Supply. The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass capacitors should be associated with the following VDD pins: 5 0.1 F 10 0.1 F 32 0.1 F A 1.0 F should be placed as close to device as is practical. Ground. Must be connected to system ground. Minimize the ground path impedance for optimal performance of this device. Manual/Automatic Clock Selection. Three level input that selects the method of input clock selection to be used. L = Manual. M = Automatic non-revertive. H = Automatic revertive. Clock Input 2. Differential input clock. This input can also be driven with a single-ended signal. Input frequency selected from a table of values. The same frequency must be applied to CKIN1 and CKIN2. Output 2 Disable/Bypass Mode Control. Controls enable of CKOUT2 divider/output buffer path and PLL bypass mode. L = CKOUT2 enabled. M = CKOUT2 disabled. H = Bypass mode with CKOUT2 enabled. Clock Input 1. Differential input clock. This input can also be driven with a single-ended signal. Input frequency selected from a table of values. The same frequency must be applied to CKIN1 and CKIN2.
5, 10, 11, 15, 32
VDD
VDD
Supply
6, 8, 31
GND
GND
Supply
9
AUTOSEL
I
3-Level
12 13
CKIN2+ CKIN2-
I
Multi
14
DBL2_BY
I
3-Level
16 17
CKIN1+ CKIN1-
I
Multi
Preliminary Rev. 0.47
7
SI5322
Table 3. SI5322 Pin Descriptions (Continued)
Pin # Pin Name I/O Signal Level Description Input Clock Select/Active Clock Indicator. If manual clock selection mode is chosen (AUTOSEL = L), this pin functions as the manual input clock selector. This input is internally deglitched to prevent inadvertent clock switching during changes in the CS input state. 0 = Select CKIN1. 1 = Select CKIN2. If automatic clock selection mode is chosen (AUTOSEL = M or H), this pin indicates which of the two input clocks is currently the active clock. If alarms exist on both CKIN1 and CKIN2, indicating that the digital hold state has been entered, CA will indicate the last active clock that was used before entering the hold state. 0 = CKIN1 active input clock. 1 = CKIN2 active input clock. Bandwidth Select. Three level inputs that select the DSPLL closed loop bandwidth. Detailed operations and timing characteristics for these pins may be found in the Any-Rate Precision Clock Family Reference Manual. Multiplier Select. Three level inputs that select the input clock and clock multiplication ratio, depending on the FRQTBL setting. Consult the Any-Rate Precision Clock Family Reference Manual or DSPLLsim configuration software for settings, both available for download at www.silabs.com/timing. Signal Format Select. Three level inputs that select the output signal format (common mode voltage and differential swing) for both CKOUT1 and CKOUT2. Valid settings include LVPECL, LVDS, and CML. Also includes selections for CMOS mode, tristate mode, and tristate/sleep mode. SFOUT[1:0] HH 33 30 SFOUT0 SFOUT1 I 3-Level HM HL MH MM ML LH LM LL Signal Format Reserved Reserved CML LVPECL Reserved LVDS CMOS Tristate/Sleep Reserved
21
CS_CA
I/O
LVCMOS
23 22
BWSEL1 BWSEL0
I
3-Level
27 26 25 24
FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0
I
3-Level
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Preliminary Rev. 0.47
SI5322
Table 3. SI5322 Pin Descriptions (Continued)
Pin # Pin Name I/O Signal Level Description Clock Output 2. Differential output clock with a frequency selected from a table of values. Output signal format is selected by SFOUT pins. Output is differential for LVPECL, LVDS, and CML compatible modes. For CMOS format, both output pins drive identical single-ended clock outputs. Clock Output 1. Differential output clock with a frequency selected from a table of values. Output signal format is selected by SFOUT pins. Output is differential for LVPECL, LVDS, and CML compatible modes. For CMOS format, both output pins drive identical single-ended clock outputs. No Connect. These pins must be left unconnected for normal operation. Ground Pad. The ground pad must provide a low thermal and electrical impedance to a ground plane.
34 35
CKOUT2- CKOUT2+
O
Multi
29 28
CKOUT1- CKOUT1+
O
Multi
7, 18, 19, 20, 36 GND PAD
NC
--
--
GND
GND
Supply
Preliminary Rev. 0.47
9
SI5322
3. Ordering Guide
Ordering Part Number SI5322-B-GM Package 36-Lead 6 x 6 mm QFN Temperature Range -40 to 85 C
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Preliminary Rev. 0.47
SI5322
4. Package Outline: 36-Lead QFN
Figure 2 illustrates the package details for the SI5322. Table 4 lists the values for the dimensions shown in the illustration.
Figure 2. 36-Pin Quad Flat No-lead (QFN)
Table 4. Package Dimensions
Symbol Min A A1 b D D2 e E E2 3.95 3.95 0.80 0.00 0.18 Millimeters Nom 0.85 0.01 0.23 6.00 BSC 4.10 0.50 BSC 6.00 BSC 4.10 4.25 4.25 Max 0.90 0.05 0.30 L aaa bbb ccc ddd eee Symbol Min 0.50 -- -- -- -- -- -- Millimeters Nom 0.60 -- -- -- -- -- -- Max 0.75 12 0.10 0.10 0.05 0.10 0.05
Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC outline MO-220, variation VJJD. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
Preliminary Rev. 0.47
11
SI5322
5. Recommended PCB Layout
Figure 3. PCB Land Pattern Diagram
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Preliminary Rev. 0.47
SI5322
Table 5. PCB Land Pattern Dimensions
Dimension e E D E2 D2 GE GD X Y ZE ZD -- -- 4.00 4.00 4.53 4.53 -- 0.89 REF. 6.31 6.31 MIN 0.50 BSC. 5.42 REF. 5.42 REF. 4.20 4.20 -- -- 0.28 MAX
Notes (General): 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on IPC-SM-782 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Notes (Solder Mask Design): 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. Notes (Stencil Design): 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 4. A 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the center ground pad. Notes (Card Assembly): 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
Preliminary Rev. 0.47
13
SI5322
DOCUMENT CHANGE LIST
Revision 0.44 to Revision 0.45
Condensed format.
Revision 0.45 to Revision 0.46
Removed references to latency control, INC, and DEC in figures and text. Changed LVTTL to LVCMOS in Table 2, "Absolute Maximum Ratings," on page 3. Added Figure 1, "Typical Phase Noise Plot," on page 4. Updated "2. Pin Descriptions: SI5322". Added "5. Recommended PCB Layout".
Revision 0.46 to Revision 0.47
Removed Figure 1. "Typical Phase Noise Plot." Changed pins 11 and 15 from NC to VDD in "2. Pin Descriptions: SI5322".
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Preliminary Rev. 0.47
SI5322
NOTES:
Preliminary Rev. 0.47
15
SI5322
CONTACT INFORMATION
Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: Clockinfo@silabs.com Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
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Preliminary Rev. 0.47

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